• DocumentCode
    3600641
  • Title

    AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches

  • Author

    Mittal, Sparsh ; Vetter, Jeffrey S.

  • Author_Institution
    Comput. Sci. & Math. Div., Oak Ridge Nat. Lab., Oak Ridge, TN, USA
  • Volume
    14
  • Issue
    2
  • fYear
    2015
  • Firstpage
    115
  • Lastpage
    118
  • Abstract
    Recently, researchers have explored way-based hybrid SRAM-NVM (non-volatile memory) last level caches (LLCs) to bring the best of SRAM and NVM together. However, the limited write endurance of NVMs restricts the lifetime of these hybrid caches. We present AYUSH, a technique to enhance the lifetime of hybrid caches, which works by using data-migration to preferentially use SRAM for storing frequently-reused data. Microarchitectural simulations confirm that AYUSH achieves larger improvement in lifetime than a previous technique and also maintains performance and energy efficiency. For single, dual and quad-core workloads, the average increase in cache lifetime with AYUSH is 6.90, 24.06 and 47.62×, respectively.
  • Keywords
    SRAM chips; cache storage; AYUSH; SRAM-NVM hybrid caches; data-migration; device lifetime; energy efficiency; last level caches; microarchitectural simulation; nonvolatile memory; write endurance; Benchmark testing; Cache memory; Energy loss; Nonvolatile memory; Radiation detectors; Random access memory; SRAM; Non-volatile memory (NVM); SRAM-NVM cache; device lifetime; hybrid cache; write endurance;
  • fLanguage
    English
  • Journal_Title
    Computer Architecture Letters
  • Publisher
    ieee
  • ISSN
    1556-6056
  • Type

    jour

  • DOI
    10.1109/LCA.2014.2355193
  • Filename
    6892940