Optimizing the Use of STT-RAM in SSDs Through Data-Dependent Error Tolerance

This brief presents a design strategy for spin-transfer torque (STT)-RAM to reduce the error-tolerance redundancy overhead and increase effective storage capacity without sacrificing its reliability. The key is to cohesively exploit the run-time data characteristics (e.g., access unit length and access frequency) and the fundamental read disturbance versus sensing error tradeoff in STT-RAM. It presents three specific data-dependent error-tolerance design techniques, and demonstrates their effectiveness in the context of using STT-RAM to replace DRAM in solid-state drives. Based on detailed modeling/simulations down to 22-nm node, we showed that these design solutions can increase the effective STT-RAM storage capacity by 26%, compared with conventional design practice.