Title :
Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
This paper describes a new model for a set of test sequences where a set S is described by a single functional test sequence T. Using this model, a procedure that compacts T compacts all the sequences in S simultaneously. This enhances the ability of the procedure to compact the set compared with procedures that consider the sequences in the set individually. It also allows the test sequences in S to be redefined. If different sequences in S have substantially different lengths, repartitioning T allows new sequences with more uniform lengths to be obtained. After repartitioning, additional test compaction can be achieved. This paper describes a test compaction procedure that includes these operations based on the modeling of a set as a single sequence.
Keywords :
circuit testing; fault diagnosis; functional analysis; logic testing; set theory; repartitioning; set modeling; single functional test sequence; stuck-at fault; test compaction; Circuit faults; Clocks; Compaction; Computational modeling; Silicon; Vectors; Very large scale integration; Finite-state machines; functional test sequences; test compaction; test generation; test generation.;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2014.2370751