CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning

Author

Zamanlooy, Babak ; Mirhassani, Mitra

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada

Volume

23

Issue

11

fYear

2015

Firstpage

2540

Lastpage

2551

Abstract

Designing low noise-to-signal-ratio (NSR) structures is one of the main concerns when implementing hardware-based neural networks. In this paper, a new continuous valued number system (CVNS) multiplication algorithm for low-resolution environment is proposed with accurate results. Using the proposed CVNS multiplication algorithm, VLSI implementation of a high-resolution mixed-signal CVNS synapse multiplier for neurochips with on-chip learning is realized. The proposed CVNS multiplication algorithm provides structures with lower NSR. Therefore, the proposed CVNS multiplication algorithm can be exploited to design robust CVNS Adaline for neurochips with on-chip learning.

Keywords

VLSI; learning (artificial intelligence); neural nets; number theory; CVNS multiplication algorithm; CVNS synapse multiplier; NSR structures; VLSI implementation; continuous valued number system multiplication algorithm; hardware-based neural networks; high-resolution mixed-signal CVNS synapse multiplier; noise-to-signal-ratio structures; on-chip learning; robust CVNS Adaline; robust neurochips; Algorithm design and analysis; Mirrors; Neural networks; Robustness; System-on-chip; Transistors; Very large scale integration; Continuous valued number system (CVNS); multiplier; neural networks; neurochips; noise-to-signal-ratio (NSR); on-chip learning; on-chip learning.;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2014.2367496

Filename

6975214