Noise Modeling and Analysis of SAR ADCs

A generic statistical model for calculating input-referred noise of an analog-to-digital converter (ADC) impaired by thermal noise is proposed. Based on this model, detailed statistical analyses are performed on three successive approximation register (SAR) ADCs and the analytical results obtained are verified with Monte Carlo simulations. To compare the input-referred noise of different SAR ADC architectures, a noise gain factor is proposed, which relates the noise at the comparator input (top plate of capacitor array) to that at the ADC input. The noise gain factors are computed and compared for all three ADCs analyzed. The model and methodology presented in this paper can be applied to various ADC architectures for circuit design and optimization.