A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in m CMOS

In this brief, a 14-bit 500 MS/s current-steering digital-to-analog converter (DAC) is proposed, which applies the novel grouped random rotation thermometer code (GRTC) and the differential-quad switching (DQS) and has good dynamic performance without calibrations. The GRTC suppresses the harmonics caused by element mismatches, while the DQS reduces the input-code transition-dependent distortion to achieve a high spurious-free dynamic range (SFDR). A unit current cell with an intrinsic precision of 12 bits rather than 14 bits is used to reduce the active area, and the simple diagonal structure with a common-centroid layout is adopted to reduce the gradient error. The measured SFDR of the proposed DAC is more than 80 dBc below 35 MHz and better than 68 dBc over the entire Nyquist bandwidth. The power consumption of the DAC core is only 67.7 mW at 500 MS/s. The proposed DAC has been implemented in the Semiconductor Manufacturing International Corporation (SMIC) 0.18-μm CMOS process and occupies an active area of only 0.55 mm².