Author_Institution :
Coll. of Inf. Eng., Shenzhen Univ., Shenzhen, China
Abstract :
A new boost bulk-driven sense-amplifier-based flip-flop (BBDSAFF) is presented. First, thanks to the boost and bulk-driven technique, the BBDSAFF consumes much lower power and can operate normally in the ultra-wide voltage range. Secondly, the adopted pseudo-PMOS dynamic technique in the RS latch output stage can greatly reduce the delay and improve the driving capability. The simulation results show advantages of high-speed, low power dissipation and very small and symmetrical rise/fall delay. Under the same simulation conditions, power dissipation, delay and PDP of the Strollo sense-amplifier-based flip-flop is 31 μW, 107 ps and 3.32 fJ whereas that of the proposed bulk-driven SAFF is 29 μW, 94 ps and 2.73 fJ. This low power consumption and high-speed BBDSAFF can be applied in various fields, such as ultra-dynamic voltage scaling VLSI, circuits, low power dissipation counter-clock systems and microprocessors.
Keywords :
amplifiers; flip-flops; BBDSAFF; PDP; RS latch output stage; Strollo sense-amplifier-based flip-flop; boost bulk-driven sense-amplifier flip-flop; counter-clock system; energy 2.73 fJ; energy 3.32 fJ; microprocessor; power 29 muW; power 31 muW; power dissipation; pseudoPMOS dynamic technique; symmetrical rise/fall delay; time 107 ps; time 94 ps; ultradynamic voltage scaling VLSI circuit;