Title :
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects
Author :
Shi-Yu Huang ; Meng-Ting Tsai ; Zeng-Fu Zeng ; Tsai, Kun-Han Hans ; Wu-Tung Cheng
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a number of distinct features. First, it can target not only catastrophic faults, but also timing faults. Second, it can be applied to general multi-pin interconnects and it can be applied to repair an interposer with multiple faulty interconnects. Third, it can perform the test-and-then-repair flow on-the-fly, and thereby eliminating the overhead of extra repair storage incurred in previous methods.
Keywords :
built-in self test; integrated circuit interconnections; integrated circuit reliability; 2.5D integrated circuit; catastrophic faults; die-to-die interconnects; faulty interposer; general multipin interconnects; multichip integration process; multiple faulty interconnects; test-and-then-repair flow; timing faults; timing-aware built-in self-repair; Circuit faults; Integrated circuit interconnections; Maintenance engineering; Receivers; Redundancy; Switches; 2.5-D Stacked IC; 2.5-D stacked integrated circuit (IC); Built-In Self-Repair; Built-In Self-Test; Interposer; Post-bond Test; Pulse-Vanishing Test; Timing Fault; built-in self-repair (BISR); built-in self-test; interposer; post-bond test; pulse-vanishing test (PV-Test); timing fault;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2015.2432131