DocumentCode
3602729
Title
Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values
Author
Erb, Dominik ; Kochte, Michael A. ; Reimer, Sven ; Sauer, Matthias ; Wunderlich, Hans-Joachim ; Becker, Bernd
Author_Institution
Univ. of Freiburg, Freiburg, Germany
Volume
34
Issue
12
fYear
2015
Firstpage
2025
Lastpage
2038
Abstract
Unknown (X) values emerge during the design process as well as during system operation and test application. X-sources are for instance black boxes in design models, clock-domain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or binary decision diagram-based reasoning may fail to generate test patterns or to prove faults untestable. This paper proposes the first efficient stuck-at and transition-delay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal pessimism of conventional algorithms when X-values are considered by mapping the test generation problem to the SAT of quantified Boolean formulas. Experiments on ISCAS benchmarks and larger industrial circuits investigate the increase in fault coverage for conventional deterministic and potential detection requirements for both randomized and clustered X-sources.
Keywords
Boolean algebra; analogue-digital conversion; binary decision diagrams; fault diagnosis; logic circuits; logic testing; Boolean satisfiability; ISCAS benchmark; QBF-based test pattern generation; SAT; X-value; analog-to-digital converters; binary decision diagram; clock-domain boundaries; clustered X-source; conventional test generation algorithm; design model; design process; fault activation; fault testability; fault untestability; industrial circuits; quantified Boolean formula; randomized X-source; structural algorithm; stuck-at fault test generation algorithm; transition-delay fault test generation algorithm; uninitialized sequential elements; well-defined logic value; Automatic test pattern generation; Circuit faults; Cognition; Computational modeling; Encoding; Integrated circuit modeling; Logic gates; ${X}$ -values; ATPG; Automatic test pattern generation (ATPG); QBF; SAT; Unknown values; X-values; quantified Boolean formula (QBF); satisfiability (SAT); stuck-at fault; transition-delay fault; unknown values;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2015.2440315
Filename
7116523
Link To Document