Ultrahigh Density Memristor Neural Crossbar for On-Chip Supervised Learning

Although there are many candidates for future computing systems, memristor-based neural crossbar (NC) is considered especially promising, thanks to their low power consumption, high density, and fault tolerance. However, their implementation is still hindered by the limitations of CMOS neuron and learning cells. In this paper, we present a memristor-based NC that implements on-chip supervised learning. Instead of using a standard CMOS neuron, a simple CMOS inverter realizes the activation function. More importantly, we propose a compact learning cell that consists of a crossbar latch of two antiparallel oriented binary memristors. This design allows for higher density integration and could be naturally extended to a multilayer neural network. Using the CMOS 40-nm design kit and a physics-based compact model of high-performance ferroelectric tunnel memristor, we performed transient simulations to validate the function of the proposed neural crossbar. Then, we construct a multilayer NC by cascading monolayer networks; thereby, enabling the network to learn nonlinearly separable functions (e.g., XOR function). Finally, the fault tolerance is evaluated with Monte Carlo simulation. Analysis of simulation results demonstrates promising applications of our proposed neural crossbar for on-chip supervised learning.