• DocumentCode
    3603826
  • Title

    Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture

  • Author

    Jinook Song

  • Author_Institution
    Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
  • Volume
    62
  • Issue
    10
  • fYear
    2015
  • Firstpage
    967
  • Lastpage
    971
  • Abstract
    This brief presents a new multistage noise-shaping (MASH) structure that has less hardware by applying partially folded architecture. A folded MASH architecture that exploits adders in half is introduced, and the proposed architecture combines the folded MASH architecture and the conventional MASH architecture. The noise power spectrum of the proposed architecture is mathematically analyzed and the noise-shaping capability of the MASH architecture is preserved.
  • Keywords
    adders; delta-sigma modulation; MASH delta-sigma modulator; MASH structure; hardware reduction; multistage noise shaping; noise power spectrum; partially folded architecture; Frequency synthesizers; Hardware; Multi-stage noise shaping; Noise cancellation; Quantization (signal); Registers; Delta-Sigma Modulator (DSM); Delta-sigma modulator (DSM); Fractional-N Frequency Synthesizer; Multistage Noise Shaping (MASH); fractional- $N$ frequency synthesizer; multistage noise shaping (MASH);
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2015.2458034
  • Filename
    7161333