DocumentCode
3603991
Title
Simulation of ESD Thermal Failures and Protection Strategies on System Level
Author
Scheier, Stanislav ; zur Nieden, Friedrich ; Arndt, Bastian ; Frei, Stephan
Author_Institution
On-board Syst. Lab., Tech. Univ. Dortmund, Dortmund, Germany
Volume
57
Issue
6
fYear
2015
Firstpage
1309
Lastpage
1319
Abstract
In this paper, approaches for the modeling and simulation of thermal destruction of ICs due to ESD are discussed from a system point of view. Considered systems consist of ESD generator, PCB, protection element, and IC. A direct connection between the ESD generator and the system is always assumed. For the modeling of an IC ESD destruction, the electric behavior model of an IC pin to ground or supply is extended with a thermal destruction model. The thermal model consists mainly of a thermal resistance and a thermal capacitance. When structure temperature reaches a threshold, a failure is assumed. All needed model parameters can be found with a set of measurements and tests. No internal knowledge of the IC or protection element structures is required. The methodology was applied to several ICs, protection elements, and system structures with emphasis on automotive electronics. All needed component model parameters were generated from measurements. Models and parameter measurements are described. Results from the system simulation were compared to system test results with hardware. In most cases, the simulation could predict well the destruction behavior of a system. Thermal failure and safe operating area prediction quality are compared. The described simulation method helps with selection of protection strategies and optimization of system ESD robustness.
Keywords
electrostatic discharge; integrated circuit reliability; ESD generator; ESD thermal failures; IC thermal destruction; PCB; protection element; safe operating area prediction quality; system level protection strategies; Capacitance; Current measurement; Electrostatic discharges; Generators; Integrated circuit modeling; Temperature measurement; Electrostatic discharge (ESD); overcurrent destruction/failure; overcurrent destruction/failure; overvoltage destruction/failure; overvoltage destruction/failure; safe operating area (SOA); system-level ESD; thermal destruction/failure criterion; thermal destruction/failure criterion;
fLanguage
English
Journal_Title
Electromagnetic Compatibility, IEEE Transactions on
Publisher
ieee
ISSN
0018-9375
Type
jour
DOI
10.1109/TEMC.2015.2442623
Filename
7166318
Link To Document