Analytical Model and New Structure of the Variable- Dielectric Trench LDMOS With Improved Breakdown Voltage and Specific ON-Resistance

A novel Silicon-on-Insulator laterally double-diffused metal-oxide-semiconductor transistor with ultralow specific ON-resistance (R_ON,sp) is proposed, and its analytical model for the breakdown voltage (BV) is presented. The device features a variable-k dielectric trench and a p-pillar beside the trench (VK-P). First, the VK trench induces additional field peaks and thus significantly increases the average electric field (E-field) strength. Second, the low-k dielectric in the upper trench leads to a high E-field strength, enabling a shortened device pitch to support the high BV. Third, the p-pillar extending from the p-body to the trench bottom not only acts as the vertical junction termination extension, but also forms the enhanced vertical reduced surface field effect, which further modulates the E-field distribution and increases the drift doping concentration. The BV and R_ON,sp are, therefore, greatly improved. At 600 V class BV, the VK-P LDMOS reduces the R_ON,sp by 54% compared with the uniform-k trench LDMOS. An analytical BV model taking account of influence of the VK dielectric trench is presented for the first time. The analytical results agree well with the simulated results.