• DocumentCode
    3604846
  • Title

    Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

  • Author

    Baturone, Iluminada ; Prada-Delgado, Miguel A. ; Eiroa, Susana

  • Author_Institution
    Inst. de Microelectron. de Sevilla, Univ. de Sevilla, Sevilla, Spain
  • Volume
    10
  • Issue
    12
  • fYear
    2015
  • Firstpage
    2653
  • Lastpage
    2668
  • Abstract
    This paper presents a method to simultaneously improve the quality of the identifiers, secret keys, and random numbers that can be generated from the start-up values of standard static random access memories (SRAMs). The method is based on classifying memory cells after evaluating their start-up values at multiple measurements in a registration phase. The registration can be done without unplugging the device from its application context, and with no need for a complex laboratory setup. The method has been validated experimentally with standard low-power SRAM modules in two different application specific integrated circuits (ASICs) fabricated with the 90-nm TSMC technology. The results show that with a simple registration the length of the identifiers can be reduced by 45%, the worst case bit error probability (which defines the complexity of the error correcting code needed to recover a secret key) can be reduced by 64%, and the worst case minimum entropy value is improved, thus reducing the number of bits that have to be processed to obtain full entropy by 81%. The method can be applied to standard digital designs by controlling the external power supply to the SRAM using software or by incorporating simple circuitry in the design. In the latter case, a module for implementing the method in an ASIC designed in the 90-nm TSMC technology occupies an active area of 42, 025 μm2.
  • Keywords
    SRAM chips; application specific integrated circuits; low-power electronics; private key cryptography; random number generation; ASIC; TSMC technology; application context; application specific integrated circuits; error correcting code complexity; external power supply control; identifier generation improvement; identifier length; identifier quality improvement; memory cells; random numbers; registration phase; secret keys; standard digital designs; standard low-power SRAM modules; standard static random access memories; start-up value evaluation; worst case bit error probability; worst case minimum entropy value improvement; Entropy; Error correction codes; High definition video; NIST; Random access memory; Reliability; PUFs; SRAMs; hardware security; random numbers;
  • fLanguage
    English
  • Journal_Title
    Information Forensics and Security, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1556-6013
  • Type

    jour

  • DOI
    10.1109/TIFS.2015.2471279
  • Filename
    7217837