DocumentCode :
3605099
Title :
Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
Author :
Pinillos Gimenez, Salvador ; Salerno Galembeck, Egon Henrique ; Renaux, Christian ; Flandre, Denis
Author_Institution :
Dept. of Electr. Eng., Univ. Center of FEI, São Bernardo do Campo, Brazil
Volume :
15
Issue :
4
fYear :
2015
Firstpage :
626
Lastpage :
628
Abstract :
The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), named OCTO SOI MOSFETs (OSMs), in relation to the hexagonal [diamond SOI MOSFETs (DSMs)] and the standard (rectangular conventional SOI MOSFETs) ones regarding the same bias conditions. The devices were manufactured with a 1-μm fully depleted SOI complementary MOS (CMOS) technology. The main experimental findings demonstrate that OSM is capable of keeping active the longitudinal corner effect and the PArallel connection of MOSFET with Different channel Lengths Effect (PAMDLE) in its structure at high-temperature conditions, and consequently, it maintains its remarkably better electrical performance in comparison with the standard SOI MOSFET, mainly its capacity to reduce the leakage drain current, without causing any extra burden to the current planar SOI CMOS technology in relation to DSMs.
Keywords :
CMOS integrated circuits; MOSFET; diamond; silicon-on-insulator; OCTO SOI MOSFET; OSM; PAMDLE; Si; diamond SOI MOSFET; fully-depleted SOI CMOS technology; fully-depleted SOI complementary MOS technology; high-temperature effects; high-temperature environment; leakage drain current; longitudinal corner effect; octagonal layout; parallel connection-MOSFET-different channel length effect; planar SOI CMOS technology; planar SOI MOSFET; rectangular conventional SOI MOSFET; silicon-on-insulator metal-oxide-semiconductor field-effect transistors; size 1 mum; standard SOI MOSFET; CMOS integrated circuits; CMOS technology; Diamonds; Layout; Logic gates; MOSFET; Standards; LCE effect and PAMDLE effect; OCTO layout style; high temperature environment; high-temperature environment; leakage drain current;
fLanguage :
English
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
Publisher :
ieee
ISSN :
1530-4388
Type :
jour
DOI :
10.1109/TDMR.2015.2474739
Filename :
7229309
Link To Document :
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