Design of new low-noise and low-power CMOS differential pair

A novel structure of a CMOS differential pair is presented, which is suitable for low supply voltages and low power consumption as well as a much higher gain than that of a conventional differential pair. This structure is based on the new technique of composite transistors. The need for the design of integrated circuits at low voltage, with low power consumption and how this constraint is reflected in the design of digital and analogue integrated circuits are demonstrated.