DEC-cache: dynamically electing candidate cache for low power utilising hearing policy

On-chip cache memory is one of the largest power consumers in modern microprocessors. A dynamic way prediction scheme utilising a hearing policy is proposed for a low-power level-one cache design that handles power limit issues. The high prediction accuracy of the dynamically electing candidate (DEC)-cache helps to prevent large miss penalties. Owing to the high prediction accuracy, the experimental results show that the DEC-cache structure improves the energy-delay product by 26% compared with the existing buffered dual-mode cache.