Investigation of RC parasitics considering middle-of-the-line in si-bulk FinFETs for Sub-14-nm node logic applications

In this brief, we systematically investigated the effects of fin pitch (FP) and fin height (H_fin) on parasitic resistances and capacitances to achieve the best RC delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The RC delays were directly extracted from the fully calibrated technology computer aided design I-V/C-V simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the RC delay likewise increased due to greater C_gg. On the other hand, the RC delay mostly decreased due to greater ON-current as the H_fin increased. The RC delay with different power supply voltages (V_DD = 0.55 and 0.75 V) was also studied to see the effect of V_DD scaling. Finally, a selective deposition was suggested to improve the RC delay about 13%.