DocumentCode :
3606368
Title :
An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems
Author :
Wei-Cheng Sun ; Wei-Hsuan Wu ; Chia-Hsiang Yang ; Yeong-Luh Ueng
Author_Institution :
Inst. of Commun. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
62
Issue :
10
fYear :
2015
Firstpage :
2512
Lastpage :
2522
Abstract :
This paper presents a high-throughput, area-efficient and energy-efficient iterative detection and decoding (IDD) receiver for low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems. A layered non-resetting IDD technique is used to minimize the number of inner iterations for a required error performance. An area-efficient minimum mean-square error with parallel interference cancellation (MMSE-PIC) detector is devised to simplify matrix inversion. A detector-decoder interface that is used to exchange soft messages efficiently is proposed. Given the throughput specifications, inner and outer loops are optimally combined to maximize the error performance. The design specifications defined in the IEEE 802.11n standard are adopted as the design target. A 4 × 4 antenna configuration with BPSK, QPSK, 16-QAM modulations are realized in silicon. The designs that support 64-QAM and 256-QAM modulations are also demonstrated for comparison with prior work. Fabricated in 40 nm technology, the chip integrates 998k logic gates in 1.33 mm2 and achieves a maximum throughput of 794 Mb/s. The chip dissipates 135 mW at 0.9 V, achieving an energy efficiency of 170 pJ/bit.
Keywords :
MIMO communication; iterative decoding; least mean squares methods; low-power electronics; matrix inversion; parity check codes; phase shift keying; quadrature amplitude modulation; radio receivers; signal detection; wireless LAN; 16-QAM modulation; 256-QAM modulation; 64-QAM modulation; BPSK modulation; IEEE 802.11n standard; LDPC coded MIMO systems; QPSK modulation; area efficient IDD; bit rate 794 Mbit/s; energy efficient IDD; iterative decoding receiver; iterative detection receiver; low density parity check code; matrix inversion; minimum mean square error detector; multiple input multiple output systems; nonresetting IDD technique; parallel interference cancellation detector; power 135 mW; soft message; voltage 0.9 V; Decoding; Detectors; Iterative decoding; MIMO; Receivers; Throughput; CMOS digital integrated circuits; iterative detection and decoding (IDD); low-density parity-check (LDPC) codes; soft-input soft-output (SISO) MIMO detector;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2015.2468998
Filename :
7272776
Link To Document :
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