Definition of an Architecture to Configure Artificial Neural Networks Topologies Using Partial Reconfiguraton in FPGA

Artificial Neural Networks (ANNs) competence in generalization and reconfigurable hardware using provide a solid base to developing critical embedded systems, capable of efficiently adapt itself as requirements change. Different level adaptation, from physical level up to system level, can be combined to provide efficient solutions using FPGA. So, this work aims to define a novel architecture to configure ANNs topologies using partial FPGA reconfiguration. NEURON block has been described using fixed-point notation and applying partial reconfiguration to load partial bitstreams of sigmoid and hiperbolic tangent functions, as well as dynamically inserting and removing NEURON blocks on the net, this way it is possible to configure MultiLayer Perceptron (MLP) networks with different topologies, using partial bitstreams in reconfigurable areas. It is conceived that, using this kind of hardware facilitates embedding applications using different topologies, MLP ANNs, easily reconfigurable on the field.