Novel Silicon on Insulator Monolithic Active Pixel Structure With Improved Radiation Total Ionizing Dose Tolerance and Reduced Crosstalk Between Sensor and Electronics

This paper introduces an advanced silicon on insulator (SOI) monolithic active pixel structure that leaves small empty volumes (interspace structure) under the SOI electronics wafer to mitigate the back-gate effect and implements silicon sidewall around the complementary metal oxide semiconductor (CMOS) electronics. The interspaces are produced by etching gaps in the oxide grown on top of the sensor wafer (buried oxide, BOX) and aligned with the CMOS channels in the electronics wafer above. The silicon sidewall surrounding the CMOS electronics is connected to the conductor layer. Two-dimensional and three-dimensional physical level simulations are presented to compare this novel structure with the nested well structure and double SOI structure. The results demonstrate that the proposed design could eliminate radiation total ionizing dose effects and reduce the parasitic capacitance between the electronics and sensor. Besides, the impact of varying the applied bias voltage and the p-well dimension on charge collection efficiency has also been studied.