Chip Warpage Induced by Tapered Through-Silicon Vias: A Numerical Analysis

Author

Dou, J. ; Shen, Y.-L.

Author_Institution

Dept. of Mech. Eng., Univ. of New Mexico, Albuquerque, NM, USA

Volume

15

Issue

4

fYear

2015

Firstpage

629

Lastpage

632

Abstract

This paper concerns chip warpage caused by thermal expansion mismatch between tapered copper (Cu) through-silicon vias (TSVs) and the surrounding silicon (Si) matrix. Systematic numerical finite-element modeling is performed to simulate the periodic array of Cu TSVs. It is demonstrated that significant chip curvature can develop as a result of the tapered TSV geometry. The effects of taper angle, diameter, and density of TSVs; wafer thickness; and intermediate layers between Cu and Si are investigated.

Keywords

copper; finite element analysis; integrated circuit testing; thermal expansion; thermal stresses; three-dimensional integrated circuits; chip curvature; chip warpage; numerical analysis; periodic array simulation; silicon matrix; systematic numerical finite element modeling; tapered TSV geometry; tapered copper through-silicon vias; thermal expansion mismatch; Geometry; Reliability; Silicon; Stress; Thermal stresses; Three-dimensional displays; Through-silicon vias; Through-silicon vias; chip warpage; modeling; thermal stress;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2015.2482488

Filename

7277072