• DocumentCode
    3607132
  • Title

    Decoder architecture for generalised concatenated codes

  • Author

    Spinner, Jens ; Freudenberger, Ju?Œ?†rgen

  • Author_Institution
    Inst. for Syst. Dynamics (ISD), HTWG Konstanz Univ. of Appl. Sci., Konstanz, Germany
  • Volume
    9
  • Issue
    5
  • fYear
    2015
  • Firstpage
    328
  • Lastpage
    335
  • Abstract
    This paper proposes a pipelined decoder architecture for generalised concatenated (GC) codes. These codes are constructed from inner binary Bose-Chaudhuri-Hocquenghem (BCH) and outer Reed-Solomon codes. The decoding of the component codes is based on hard decision syndrome decoding algorithms. The concatenated code consists of several small BCH codes. This enables a hardware architecture where the decoding of the component codes is pipelined. A hardware implementation of a GC decoder is presented and the cell area, cycle counts as well as the timing constraints are investigated. The results are compared to a decoder for long BCH codes with similar error correction performance. In comparison, the pipelined GC decoder achieves a higher throughput and has lower area consumption.
  • Keywords
    BCH codes; Reed-Solomon codes; binary codes; concatenated codes; decoding; error correction codes; GC codes; cell area; component codes; cycle counts; error correction performance; generalised concatenated codes; hard decision syndrome decoding algorithms; hardware architecture; inner binary Bose-Chaudhuri-Hocquenghem codes; outer Reed-Solomon codes; pipelined decoder architecture; small BCH codes; timing constraints;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices Systems, IET
  • Publisher
    iet
  • ISSN
    1751-858X
  • Type

    jour

  • DOI
    10.1049/iet-cds.2014.0278
  • Filename
    7279045