• DocumentCode
    3607180
  • Title

    Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing

  • Author

    Zhiting Yan ; Guanghui He ; Yifan Ren ; Weifeng He ; Jianfei Jiang ; Zhigang Mao

  • Author_Institution
    Sch. of Electron. Inf. & Electr. Eng., Shanghai Jiao Tong Univ., Shanghai, China
  • Volume
    62
  • Issue
    11
  • fYear
    2015
  • Firstpage
    2706
  • Lastpage
    2717
  • Abstract
    This paper proposes a flexible dual-mode soft-output multiple-input multiple-output (MIMO) detector to support open-loop and closed-loop in Chinese enhanced ultra high throughput (EUHT) wireless local area network (LAN) standard. The proposed detector uses minimum mean square error (MMSE) sorted QR decomposition (MMSE-SQRD) to produce channel preprocessing result, which is realized by a modified systolic array architecture with concurrent sorting. Moreover, the adopted square-root MMSE algorithm for closed-loop reuses MMSE-SQRD preprocessing to largely save hardware overhead. In addition, an optimized K-Best detection algorithm is proposed for open-loop, which increases throughput by odd-even parallel sorting and produces high quality soft-output with discarded paths (DPs). A flexible VLSI architecture is designed for the proposed dual-mode detector, which supports 1×1 ~ 4×4 antennas and BPSK ~ 64-QAM modulation configuration. Implemented in SMIC 65 nm CMOS technology, the detector is capable of running at 550 MHz, which has a maximum throughput of 2.64 Gb/s for K-Best detection and 3.3 Gb/s for linear MMSE detection. The proposed detector is competitive to recent published works and meets the data-rate requirement of the EUHT standard.
  • Keywords
    CMOS integrated circuits; MIMO communication; UHF detectors; VLSI; mean square error methods; phase shift keying; quadrature amplitude modulation; systolic arrays; wireless LAN; BPSK; CMOS technology; Chinese EUHT WLAN; MMSE-SQRD; QAM modulation; SMIC; binary phase shift keying; channel preprocessing; closed-loop reuse; complementary metal oxide semiconductor; enhanced ultra high throughput; flexible VLSI architecture; flexible dual-mode soft-output MIMO detector; frequency 550 MHz; k-best detection algorithm; minimum mean square error; multiple-input multiple-output detector; odd-even parallel sorting; quadrature amplitude modulation; size 65 nm; sorted QR decomposition; systolic array; very large scale integration; wireless local area network; Detection algorithms; Detectors; MIMO; Sorting; Standards; Throughput; Very large scale integration; Channel preprocessing; K-Best detection; minimum mean square error (MMSE) detection; multiple-input multiple-output (MIMO); sorted QR decomposition (SQRD);
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2015.2479055
  • Filename
    7279190