New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications

Sign-extension of operands in the shift-add network of multiple constant multiplication (MCM) results in a significant overhead in terms of hardware complexity as well as computation time. This paper presents an efficient approach to minimize that overhead. In the proposed method, the shift-add network of an MCM block is partitioned into three types of sub-networks based on the types of fundamentals and interconnections they involve. For each type of sub-network, a scheme which takes the best advantage of the redundancy in the computation of sign-extension part is proposed to minimize the overhead. Moreover, we also propose a technique to avoid the additions pertaining to the most significant bits (MSBs) of the fundamentals. Experimental results show that the proposed method always leads to implementations of MCM blocks with the lowest critical path delay. The existing methods for the minimization of sign-extension overhead are designed particularly for single multiplication or MCM blocks of FIR filter, but the proposed method can be used to reduce the overhead of sign-extension for MCM blocks of any application. In the case of FIR filters, the proposed method outperforms other competing methods in terms of critical path delay, area-delay product (ADP), and power-delay product (PDP), as well.