DocumentCode :
3607416
Title :
Process Development and Optimization for 3 
High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level
Author :
Dingyou Zhang ; Smith, Daniel ; Kumarapuram, Gopal ; Giridharan, Rudy ; Kakita, Shinichiro ; Rabie, Mohamed A. ; Peijie Feng ; Edmundson, Holly ; England, Luke
Author_Institution :
GlobalFoundries, Malta, NY, USA
Volume :
28
Issue :
4
fYear :
2015
Firstpage :
454
Lastpage :
460
Abstract :
This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical dimension and 50 μm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 μm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.
Keywords :
electroplating; etching; integrated circuit metallisation; isolation technology; three-dimensional integrated circuits; CMOS device; TSV etch; TSV integration; copper electroplating; dielectric liner coverage; high aspect ratio via-middle through silicon vias; metal barrier; process development; process optimization; seed layer coverage; size 3 mum; size 50 mum; top entrant critical dimension; wafer level; Copper; Dielectrics; Etching; Plating; Resists; Stress; Through-silicon vias; 3D; KOZ; TSV; electroplating; etch; high aspect ratio;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2015.2485079
Filename :
7286846
Link To Document :
