Efficient very large-scale integration architecture for variable length block least mean square adaptive filter

The authors made an analysis on computational complexity of block least mean square (BLMS) finite impulse response (FIR) filter and decompose the filter computation into M sub-filters, where M = N/L, N is the filter length and L is the block-size. The proposed decomposition scheme favours time-multiplexing the filtering computation and weight-increment term computation of BLMS algorithm. Using the proposed scheme, they have derived an efficient architecture for BLMS FIR filter. The proposed structure can be reconfigured for different filter lengths with negligible overhead complexity and it supports variable convergence factor. Besides, the proposed structure has 100% hardware utilisation efficiency and its register complexity is independent of block-size. Compared with recently proposed LMS-based FIR structure the proposed structure involves L times more multipliers, proportionately less adders and the same number of registers, and it offers L times higher throughput. Application specific integrated circuit (ASIC) synthesis results show that the proposed structure for block-size 4 and filter-length 64 involve 21.4% less area-delay product (ADP) and 26.6% less energy per sample (EPS) than those of the existing structure and offers 3.8 times higher throughput.