A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs

We propose a calibration-free sensing scheme to solve the diminishing sensing margin and unstable trip-point problems of the sense amplifier caused by process, voltage, and temperature variations and by data dependency in conventional single-ended-and footless-8T SRAM designs. The key designs in this new scheme include an NMOS keeper for enlarging and uniformizing the sensing margin across operating conditions, a continuously variable trip-point sense amplifier for automatically adapting the trip-point, and a new corresponding sensing operation. The proposed scheme has been applied in the design of a 512-kb SRAM frame buffer in a video-recording SoC in 65-nm LP CMOS. For a 1-MHz operating frequency, the minimal supply voltage, Vmin, of the frame buffer is 0.45 V. At 0.48 V, the frame buffer has a minimum energy consumption of 26.5 pJ/cycle.