Title :
Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device
Author :
Tailor, Ketankumar H. ; Shrivastava, Mayank ; Gossner, Harald ; Baghini, Maryam Shojaei ; Rao, Valipe Ramgopal
Author_Institution :
Dept. of Electr. Eng., IIT Bombay, Mumbai, India
Abstract :
In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF- and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.
Keywords :
MOSFET; isolation technology; semiconductor device breakdown; MOSFET; STI type drain extended pMOS device; breakdown voltage reduction; safe operating area; shallow trench isolation; size 65 nm; triple well CMOS process; two stage breakdown; Avalanche breakdown; Breakdown voltage; Current density; Electric breakdown; Junctions; MOS devices; Semiconductor process modeling; Avalanche breakdown; Kirk effect; drain-extended MOSFET (DeMOS); input-output (I/O); input???output (I/O); parasitic bipolar triggering; safe operating area (SOA); shallow-trench isolation (STI); two-stage breakdown; two-stage breakdown.;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2015.2481899
