Title :
Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces
Author :
Gharibdoust, Kiarash ; Tajalli, Armin ; Leblebici, Yusuf
Author_Institution :
Swiss Fed. Inst. of Technol., Lausanne, Switzerland
Abstract :
A 7.5 Gb/s mixed NRZ/multi-tone (NRZ/MT) transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for an MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I/Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel response over a ±25% range. A switched-capacitor-based mixer/filter is developed to efficiently down convert and equalize the I/Q sub-bands in the RX. The core size area is 85 × 60 μm2 and 150 × 60 μm2 for the TX and RX, respectively.
Keywords :
CMOS integrated circuits; transceivers; MDB memory interfaces; NRZ/multitone transceiver; TRX; equalization circuitry; hybrid NRZ/multitone serial data transceiver; modulation frequency; multidrop bus; multidrop memory interfaces; switched capacitor; Bit error rate; Decision feedback equalizers; Mixers; Optical signal processing; Phase shift keying; Receivers; Transceivers; Decision-feedback equalizer (DFE); differential signaling; intersymbol interference (ISI); multi-drop bus (MDB); multi-tone signaling; nonreturn-to-zero (NRZ) signaling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2015.2483904