DocumentCode :
3608709
Title :
Complete 3D-Reduced Surface Field Superjunction Lateral Double-Diffused MOSFET Breaking Silicon Limit
Author :
Baoxing Duan ; Zhen Cao ; Song Yuan ; Yintang Yang
Author_Institution :
Key Lab. of Wide Band-Gap Semicond. Mater. & Devices, Xidian Univ., Xi´an, China
Volume :
36
Issue :
12
fYear :
2015
Firstpage :
1348
Lastpage :
1350
Abstract :
A new superjunction lateral double-diffused MOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) has been proposed in this letter, for the first time, with the complete three-dimensional reduced surface field (3D-RESURF). The SIPOS SJ-LDMOS along the three dimensions are subject to the electric field modulation, which achieves the complete 3D-RESURF effect. The simulated breakdown voltage (BV) for the unit length of the drift region is improved to 19.4 V/μm. The drift region with the high concentration compared with the conventional LDMOS can be depleted completely in the OFF-state to obtain the high BV. Moreover, the majority carrier accumulation can be formed to further decrease RON,sp (specific on resistance) during the ON-state operation. Three effects have been combined to SIPOS SJ-LDMOS for the superjunction ideal, electric field modulation and the majority carrier accumulation by SIPOS. The tradeoff between the BV and RON,sp has been improved to break through the silicon limit. The results show that the experimental RON,sp of SIPOS SJ-LDMOS is 18 mQ · cm2 with the tested BV of 376 V, which is less than that of 31.1 mQ · cm2 for the N-buffer SJ-LDMOS with the simulated BV of 287 V, and far less than 71.8 mQ · cm2 for the conventional LDMOS with the simulated BV of 254 V for the same drift region length of 20 μm.
Keywords :
MOSFET; elemental semiconductors; semiconductor device breakdown; silicon; 3D-RESURF effect; SIPOS SJ-LDMOS; Si; breakdown voltage; complete 3D-reduced surface field effect; drift region; electric field modulation; majority carrier accumulation; semiinsulating poly silicon; silicon limit; superjunction lateral double-diffused MOSFET; voltage 254 V; voltage 287 V; voltage 376 V; Breakdown voltage; MOS devices; MOSFET; Resistance; Silicon; LDMOS; SIPOS; Silicon Limit; Super Junction; Super junction; silicon limit;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2015.2493080
Filename :
7302547
Link To Document :
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