Abstract :
In modern design flows, technology-dependent logic optimizations consist of technology mapping and transformations applied after mapping. Advances have been made in technology mapping in the last decade. However, it is inherently an intractable problem and state-of-the-art algorithms produce suboptimal netlists in terms of area and timing. Also, during the design flow, when physical information becomes available, wire loads and net delays change the timing values at the gates. That presents opportunities for further timing and area optimization. This is accomplished by transforms such as gate sizing, gate replication, buffer optimization, restructuring and remapping, and pin permutation. In this paper, we survey algorithms for technology-dependent optimizations, along with a comparison of their relative power to optimize the netlist.
Keywords :
buffer circuits; logic CAD; logic gates; area optimization; buffer optimization; design flows; gate replication; gate sizing; net delays; pin permutation; restructuring-and-remapping; suboptimal netlists; technology mapping; technology transformations; technology-dependent logic optimization; timing optimization; timing values; wire loads; Design methodology; Flow production systems; Load modeling; Logic gates; Optimization; Buffer optimization; gate replication; gate sizing; logic synthesis; technology mapping;
