Analogue multiplier using passive circuits and digital primitives with time-mode signal representation

A new architecture to multiply signals with time-mode representations is proposed. The exponential relationship between voltage and time in an RC circuit is utilised to implement the time-mode logarithmic and exponential functions needed to realise a time-mode analogue of the translinear principle. The addition of time-mode variables is achieved through the natural progression of time equal to the sum of the input times. By combining these two techniques, an analogue multiplier can be implemented almost exclusively with passive circuits and digital primitives. Therefore, the circuit performance could benefit from CMOS scaling trends. The architecture is described, and simulation results are presented for an operational circuit implementing this approach.