Title :
Benchmarking of MoS2 FETs With Multigate Si-FET Options for 5 nm and Beyond
Author :
Agarwal, Tarun ; Yakimets, Dmitry ; Raghavan, Praveen ; Radu, Iuliana ; Thean, Aaron ; Heyns, Marc ; Dehaene, Wim
Author_Institution :
Dept. of Electr. Eng., Katholieke Univ. Leuven, Leuven, Belgium
Abstract :
In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%-45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET.
Keywords :
MOSFET; contact resistance; elemental semiconductors; molybdenum compounds; nanowires; power consumption; semiconductor device models; silicon; FET benchmarking; FinFET; MoS2; Si; atomistic two-band ballistic quantum transport; back-end-of-the-line load; bilayer FET; contact resistance; device current; energy consumption; extrinsic parasitic elements; interconnect elements; intrinsic capacitances; intrinsic parasitic elements; lateral nanowire FET; monolayer FET; multigate Si-FET options; parasitic capacitances; ring oscillator; size 5 nm; two-band model currents; vertical nanowire FET; Benchmark testing; Capacitance; Energy consumption; Field effect transistors; MOSFET; Performance evaluation; 2-D materials; MOSFET; ballisticity; benchmarking; monolayer MoS₂; monolayer MoS2; parasitic capacitances; parasitic capacitances.;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2015.2491021