Porting and Scaling Strategies for Nanoscale CMOS RHBD

Techniques are described for minimizing the number of cells in a digital logic library, scaling and porting the cells to process nodes that do not nominally support scaling, and increasing the separation of critical node pairs without unduly disrupting the design process. A new compact modular 10T compact continuously-voting latch cell reduces circuitry to conventional latch sizes, at less power, allowing modular redundancy to approach theoretical efficiency limits. The result is allows investment in low volume designs, such as but not limited to radiation hardened by design (RHBD) applications for mission critical components, to provide returns over decades-long time periods.