Dynamic Element Matching Techniques for Static and Dynamic Errors in Continuous-Time Multi-Bit $\Delta \Sigma$ Modulators

This paper presents techniques to address static and dynamic errors in high performance continuous-time (CT), ΔΣ modulators. The inter-symbol interference (ISI) model is presented and existing ISI reduction techniques are reviewed. A novel technique has been presented which can high-pass shape both static mismatch and ISI error of each element of a multi-bit DAC while decorrelating the instantaneous number of transitions from the input signal. The proposed technique can easily be extended to higher order shaping for both static mismatch and ISI errors. Simulation results show that the proposed technique can improve DAC linearity significantly in presence of both static mismatch and ISI error.