Continuous-Time Delta-Sigma ADCs With Improved Interferer Rejection

This paper reviews and analyzes the state of the art of Delta-Sigma modulators for receiver applications. Receiver ADCs require not only steadily increased bandwidth, low power and area consumption, but especially face strong interferer signals. These are outside the band of interest, but they most often determine the overall receiver dynamic range and linearity requirements. In order to avoid or at least relax explicit filtering in front of the ADC, Delta-Sigma architectures have been presented with improved robustness to interferers by filtering. This paper intends to review the motivation, to give a tutorial of the state of the art, as well as to introduce a deeper analysis for DSM with interferer robustness. For this, an introduction to the requirements of Delta-Sigma modulators in receivers is given, and a method is introduced which allows to analyze and to scale the internal states meeting the requirements of the interferer scenarios. The paper additionally analyzes state-of-the-art techniques of modulators with improved interferer rejection in order to outline more clearly their possibilities and drawbacks.