Layout and Radiation Tolerance Issues in High-Speed Links

High-speed optical links are often used in trigger and data acquisition systems of High Energy Physics (HEP) experiments for data transfer, trigger and fast control distribution. Many experiments prefer the use of commercial off-the-shelf components (COTS) if possible, in order to avoid the non-recurrent engineering (NRE) costs and risks associated with the design of application specific integrated circuits. For the mentioned reason, static random access memory-based field programmable gate arrays (SRAM-based FPGAs) are usually deployed. However they are mostly used off-detector, where little or no radiation is present, since single event upsets in the configuration memory may alter the design functionality. In order to benefit from SRAM-based FPGAs also in radiation environments expected on-detector, suitable soft-error mitigation strategies must be adopted. In this work we evaluate the design trade-offs between performance and radiation-tolerance in a high-speed fixed-latency link based on a Virtex-5 SRAM-based FPGA. We evaluate different radiation mitigation strategies. Moreover, we experimentally verify some custom-developed placement and routing rules aimed at improving the FPGA firmware robustness against configuration upsets.