Dynamic fine-grain leakage reduction using leakage-biased bitlines

Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic deactivation techniques that include the effects of deactivation energy and startup latencies, as well as long term leakage current. We present a new circuit-level technique for leakage current reduction, leakage-biased bitlines, that has low deactivation energy and fast wake-up times. We show how this technique can be applied at a fine grain within an active microprocessor and how microarchitectural scheduling policies can improve its performance. Using leakage-biased bitlines to deactivate SRAM read paths within I-cache memories saves over 24% of leakage energy and 22% of total I-cache energy when using a 70 nm process. In the register file, fine-grained read port deactivation saves nearly 50% of leakage energy and 22% of total energy independently, turning off idle register file subbanks saves over 67% of leakage energy (57% total register file energy) with no loss in performance.