Power analysis of multiplier blocks

In this study, three multiplier-blocks generated by different algorithms are analyzed for their power consumption via transition count based on their implementation on the Xilinx Virtex device. The high level Glitch-Path method, which is used for estimating the relative figures of transitions occurring at the outputs of the adders, has been refined for more accurate estimation and a new method GP Score is proposed. Several design issues are discussed regarding ways of reducing the transitions.