Current-balanced logic in submicron technology

The analysis of the current-balanced logic (CBL) in submicron technology is presented. Current-balanced logic is a low-noise logic family suitable for use in mixed-signal integrated circuits, because of the reduced supply current spikes. On entering the submicron region, the question arises as to whether the CBL will still maintain this good performance. The analysis of CBL with the simple current model of the submicron MOS transistor was carried out. The supply current is not fully compensated, but the deviation is not too high. The current spikes are still lower than in CMOS. The variation of the supply current in CBL was verified with SPICE simulation of the CBL inverter in 0.25-/spl mu/m technology. SPICE simulations were also used to compare the static and dynamic performances of the CBL and CMOS inverters.