• DocumentCode
    3614066
  • Title

    Static series-voltage noise margins of CBL, CSL and CMOS

  • Author

    A. Szabo;Z. Butkovic

  • Author_Institution
    Fac. of Electr. Eng. & Comput., Zagreb Univ., Croatia
  • Volume
    2
  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Firstpage
    587
  • Abstract
    The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in a system, whilst still operating correctly. In this work the static series-voltage noise margin of CBL (current-balanced logic), CSL (current-steering logic) and CMOS are determined and compared.
  • Keywords
    "CMOS logic circuits","Flip-flops","Circuit noise","Logic circuits","Voltage","Integrated circuit noise","Semiconductor device noise","Logic gates","Pulse inverters","Logic devices"
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2002. 9th International Conference on
  • Print_ISBN
    0-7803-7596-3
  • Type

    conf

  • DOI
    10.1109/ICECS.2002.1046236
  • Filename
    1046236
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3614066