DocumentCode :
3614320
Title :
Architectures and implementations of low-density parity check decoding algorithms
Author :
E. Yeo;B. Nikolic;V. Anantharam
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Volume :
3
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Abstract :
Architectures for low-density parity-check (LDPC) decoders are discussed, with methods to reduce their complexity. Serial implementations similar to traditional microprocessor datapaths are compared against implementations with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Several classes of LDPC codes, such as those based on irregular random graphs and geometric properties of finite fields are evaluated in terms of their suitability for VLSI implementation and performance as measured by bit-error rate. Efficient realizations of low-density parity check decoders under area, power, and throughput constraints are of particular interest in the design of communications receivers.
Keywords :
"Parity check codes","Iterative decoding","Message passing","Computer architecture","Parallel processing","Bit error rate","Throughput","Bipartite graph","Microprocessors","Galois fields"
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
Type :
conf
DOI :
10.1109/MWSCAS.2002.1187067
Filename :
1187067
Link To Document :
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