• DocumentCode
    3614362
  • Title

    On structural vs. functional testing for delay faults

  • Author

    A. Krstic; Jing-Jia Liou; Kwang-Ting Cheng;L.-C. Wang

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
  • fYear
    2003
  • fDate
    6/25/1905 12:00:00 AM
  • Firstpage
    438
  • Lastpage
    441
  • Abstract
    A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there could be a large difference in the number of structurally and functionally testable delay faults. However, this difference is usually calculated based only on logic constraints. It is unclear how this difference would change if timing constraints were taken into consideration, especially when using statistical timing models. In this paper, our goal is to better understand how structural and functional test strategies might affect the delay test quality and consequently, change our perception of the delay test results.
  • Keywords
    "Delay","Circuit testing","Circuit faults","Timing","Semiconductor device testing","Built-in self-test","Logic testing","Automatic testing","Flip-flops","Registers"
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
  • Print_ISBN
    0-7695-1881-8
  • Type

    conf

  • DOI
    10.1109/ISQED.2003.1194772
  • Filename
    1194772