Title :
Family of folded bit-serial multipliers
Author :
V.M. Ciric;I.Z. Milentijevic;O.M. Vojinovic;T.I. Tokic
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Serbia
fDate :
6/25/1905 12:00:00 AM
Abstract :
The synthesis of new family of folded bit-serial multipliers for integer multiplication is presented in this paper. Folding technique is applied to serial-parallel serial multiplier architecture. The resulting architecture can operate with operands of arbitrary length. In order to illustrate functionality of proposed architecture the preliminary results of FPGA implementation are given.
Keywords :
"Delay","Field programmable gate arrays","Circuits","Digital signal processing chips","Systolic arrays","Throughput","Very large scale integration","Public key cryptography","Elliptic curves","Galois fields"
Conference_Titel :
Telecommunications in Modern Satellite, Cable and Broadcasting Service, 2003. TELSIKS 2003. 6th International Conference on
Print_ISBN :
0-7803-7963-2
DOI :
10.1109/TELSKS.2003.1246299
