Design of self-checking combinational circuits

Very large scale integration (VLSI) technology has evolved to a level where large systems, previously implemented as printed circuit boards with discrete components, are integrated into a single integrated circuit (IC). But aggressive new chip design technologies frequently adversely effect chip reliability during functional operation. The use of concurrent error detection (CED) scheme with order to achieve the high reliability requirement of modern computer systems is becoming an important design technique. The present paper describes implementation of separable codes for detecting unidirectional error within the VLSI ICs. We address the problem of synthesizing totally self-checking (TSC) combinational circuits starting from a VHDL description. Four schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a TSC comparator. The second scheme for synthesizing combinational circuits with CED uses Berger code. The third scheme is based on Bose-Lin codes. The fourth uses parity codes on the outputs of a combinational circuit. Results concerning area overheads and operating speed decreases for twelve circuits of standard architecture, when they are implemented into circuits of FPGA and CPLD technologies, are reported in this paper.