• DocumentCode
    3614954
  • Title

    Vertical p-channel double-gate MOSFETs

  • Author

    J. Moers;S. Trellenkamp;Avd. Hart;M. Goryll;S. Mantl;P. Kordos;H. Luth

  • Author_Institution
    Inst. of Thin Films & Interfaces, Res. Center Julich, Germany
  • fYear
    2003
  • fDate
    6/25/1905 12:00:00 AM
  • Firstpage
    143
  • Lastpage
    146
  • Abstract
    Double-gate MOSFETs have drawn increasing interest within the last years because of their capability to reduce short channel effects. In this work a p-channel double-gate MOSFET layout was realised. Based on epitaxial growth and subsequent ion implantation, the p/n/p-doping profile is implemented in vertical sequence. P-channel devices with channel lengths of 50 nm and gate oxide thickness of 6.6 nm show transconductances of 480 /spl mu/S//spl mu/m, subthreshold slope of 126 mV/dec and DIBL of 80 mV/V.
  • Keywords
    "MOSFETs","Silicon","Substrates","Lithography","Ion implantation","FinFETs","Doping profiles","Boron","Transistors","Epitaxial growth"
  • Publisher
    ieee
  • Conference_Titel
    European Solid-State Device Research, 2003. ESSDERC ´03. 33rd Conference on
  • Print_ISBN
    0-7803-7999-3
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2003.1256831
  • Filename
    1256831
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3614954