A versatile structure of S31-GGA-casc switched-current memory cell with complex suppression of memorizing errors

This contribution describes the circuit structure of high precision S31-GGA-casc switched-current (SI) memory cell providing complex suppression of memorizing errors. The low-frequency relative current error caused by charge-injection and input/output conductance ratio is typically 50 ppm. Moreover, the DC current offset of this cell type is lower than 0.2 /spl mu/A within the signal range of 350 /spl mu/A. At this point, excellent DC stability was achieved by a new solution of current biasing circuitry. The cell provides optimized input/output impedance ratio which can further minimize the errors arising in a SI system. All the results were proven by circuit simulation and chip measurement. In the field of circuit testing, a new concept of high-precision current-sensing circuit was invented and it is also being described in this paper.