On maximum current estimation in CMOS digital circuits

We show the importance of accounting for supply currents on the quiet power terminal when analyzing impact of peak currents on power distribution network. The quiet power terminal is defined for any signal transition in the CMOS inverter as the contact point opposite to the (dis)charging terminal. We investigate the current dynamics on these supposedly quiet contact points, and describe their dependencies on output load and input transition times. We furthermore propose triangular model representations for the quiet terminal current and its slope; the latter necessary to enable L/spl middot/dI/dt prediction.