A 27 mW 1.1 mm/sup 2/ motion estimator for picture-rate up-converter

The gap between application-specific integrated circuits (ASICs) and general purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction set processors (ASIPs) bridge this wide gap. This work presents a design of a very long instruction word (VLIW) based ASIP for motion estimation which is used in the picture-rate up-conversion application. The ASIP meets low-power and low-cost requirements apart from providing flexibility for the application domain. It consumes 27 mW and takes an area of 1.1 mm/sup 2/ in 0.13 /spl mu/m technology for delivering motion estimation functionality for standard definition (SD) sequences at 140 fps. Motion estimator performed single scan, where for each block of 8*8 pixels evaluation is done using the set of five motion vector candidates. The evaluation criterion was the sum-of-absolute-difference (SAD) criterion with the SAD window size of 32 pixels. In order to prove the concept in silicon, an FPGA prototyping system has been used.